1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a dynamic random access memory (DRAM) which operates based on internal potentials such as a substrate potential, a cell plate potential, a precharge potential for bit line, a boosted ground potential and a boosted power supply potential.
2. Description of the Background Art
In general, semiconductor memory devices are broadly classified into volatile memories such as an RAM and non-volatile memories such as an ROM. Volatile memories are broadly classified into DRAMs and static random access memories (SRAMs). Non-volatile memories are broadly classified into a mask ROM, an EPROM, a flash memory, an EEPROM and a fuse ROM.
Since the DRAM stores data by accumulating electric charges in a capacitor of a memory cell, it requires a refresh operation. However, memory cells have a simple structure. Therefore, DRAMs having a large-scale memory capacity can be formed with a low cost.
The DRAM is formed on one semiconductor substrate, which is supplied with a negative potential Vbb. A cell plate of a capacitor is supplied with a predetermined cell plate potential Vcp. Cell plate potential Vcp is, for example, half a power supply potential, i.e., Vcc/2 or a ground potential Vss. Bit line pair is precharged to a predetermined precharge potential Vb1 before activation of a sense amplifier. Precharge potential Vb1 is, for example, the power supply potential Vcc or half the power supply potential, i.e., Vcc/2.
The same assignee as the present invention has proposed in U.S. patent application Ser. No. 08/312,968, filed Sep. 30, 1994, a so-called a voltage-boosted sense ground method for the purpose of reducing a power consumption and an access time. According to this voltage-boosted sense ground method, a boosted ground potential Vss' slightly higher than the normal ground potential Vss is supplied to an N-channel side of the sense amplifier.
In the write operation of DRAM, a word line is supplied with a boosted power supply potential Vpp higher than power supply potential Vcc. Boosted power supply potential Vpp must be higher than power supply potential Vcc by at least a threshold voltage of a transfer gate in the memory cell. When the potential of word line is boosted, sufficient electric charges are accumulated in a cell capacitor. The same assignee as the present invention has proposed, in U.S. patent application Ser. No. 08/357,007, filed Dec. 16, 1994, a technique for forming hierarchical lines supplied with such a boosted power supply potential. This technique is disclosed also in "Subthreshold-Current Reduction Circuits for Multi-Gigabit DRAM's", 1993 Symposium on VLSI Circuits Digest of Technical Papers, pp. 45-46.
(1) In connection with substrate potential Vbb
In the DRAM, electric charges accumulated in the cell capacitor leak as described above, so that the cell capacitor must be periodically refreshed. This leak is caused by the flow from the cell capacitor through the transfer gate and the flow from the cell capacitor to a substrate or a neighboring memory cell. The former is called "disturb refresh" and the latter is called "pause refresh".
FIG. 27 is a cross section showing a structure of the memory cell in the DRAM. Referring to FIG. 27, a memory cell 1 is formed on a semiconductor substrate 4. One memory cell 1 is formed of one transfer gate 2 and one cell capacitor 3. Transfer gate 2 is formed of two N-type source/drain regions 5 and a gate electrode forming a word line WL. Cell capacitor 3 is formed of a storage node 6 in contact with one of source/drain regions 5 and a cell plate 7. The other source/drain region 5 is connected to a bit line BL. When the potential of word line WL attains the boosted power supply potential Vpp, transfer gate 2 becomes conductive, and the potential of bit line BL is supplied to storage node 6. Thereby, data is stored in cell capacitor 3.
A problem of the capacitor disturb refresh will be described below. It is assumed that memory cell 1 has initially stored data at H-level. Since the potential of word line WL is at the L (logical low) level of this memory cell 1, transfer gate 2 is non-conductive. In this state, when the potential of word line WL in the neighboring memory cell attains Vpp level, the potential of word line WL of this memory cell 1 slightly rises. This is due to the fact that the mutually neighboring word lines WL are coupled together via a parasitic capacitance 8. Therefore, transfer gate 2 becomes slightly conductive, whereby a subthreshold current Isth flows through a channel region under the word line WL. In accordance with miniaturization of transfer gate 2, its threshold voltage decreases. Therefore, subthreshold current Isth increases in accordance with miniaturization of transfer gate 2. In order to overcome this problem, negative substrate potential Vbb at an allowable minimum level is applied to P-type semiconductor substrate 4 in the DRAM. The reason for this is that as substrate potential Vbb is deepened, the substrate effect increases the threshold voltage, so that subthreshold current Isth decreases.
A problem of the pause refresh will be described below. The electric charges stored in storage node 6 leak as subthreshold current Isth, and also leak to semiconductor substrate 4 via a PN junction of source/drain region 5 formed under storage node 6. Electric charges accumulated-in storage node 6 further leak to a neighboring memory cell through semiconductor substrate 4 under an element isolating film 9 such as LOCOS.
FIG. 28 is a graph showing a relationship between a pause time in refresh and the number of defective memory cell(s). As can be seen from this graph, if the substrate potential Vbb is deep, the defective memory cell appears at an area where the pause time is short. If substrate potential Vbb is shallow, the defective memory cell appear at an area where the pause time is long. Therefore, shallower substrate potential Vbb can increase the pause time. The reason for this is that as the substrate potential Vbb becomes shallow, the voltage applied to a depletion layer around source/drain regions 5 decreases, so that an electric field in the depletion layer decreases. Therefore, generation of minority carriers is suppressed, which reduces the leak current flowing from source/drain regions 5 to semiconductor substrate 4.
As described above, the leak current from the memory cell increases if substrate potential Vbb is excessively shallow or excessively deep. In the conventional DRAM, semiconductor substrate 4 is entirely supplied with substrate potential Vbb which is neither shallow nor deep so as to prevent remarkable problems relating to the disturb refresh and pause refresh. Therefore, it is impossible to prevent substantially the leak current from memory cell 1.
(2) In connection with cell plate potential Vcp and bit line precharge potential Vb1.
As described before, cell plate 7 is supplied with the potential, e.g., of Vcc/2 which is half the power supply potential. During standby, bit line BL is also supplied with the potential, e.g., of Vcc/2 which is half the power supply potential. An intermediate potential generating circuit for generating the intermediate potential Vcc/2 must have such features that its output potential is hardly influenced by variation of process conditions and its output impedance is low. A large amount of current always flows in the intermediate potential generating circuit, because a transistor functioning as a diode and a transistor at the output stage must have large sizes. This results in a problem that the intermediate potential generating circuit consumes a large amount of current.
(3) In connection with boosted ground potential Vss'
Although the voltage-boosted sense ground method described before significantly reduces the power consumption of DRAM, further reduction of the power consumption is required. In the DRAM employing the voltage-boosted sense ground method, it is necessary to reduce the test time for determining whether memory cells are accepted or not.
(4) In connection with boosted power supply potential Vpp
Although hierarchization of boosted power supply lines significantly reduces the power consumption of DRAM as described before, further reduction of power consumption is necessary. It is also necessary to check the leak current from the hierarchical segment boosted power supply lines.